1. Field of the Invention
The present invention relates to an output buffer circuit and more particularly, to an output buffer circuit applicable to high-speed logic operation using two field-effect transistors (FETs) serially connected to each other, which is preferably realized on semiconductor integrated circuits.
2. Description of the Prior Art
FIG. 1 shows a conventional output buffer circuit 31, which has first and second n-channel enhancement metal-oxide-semiconductor FETs (MOSFETs) 41 and 42 serially connected to each other. The MOSFETs 41 and 42 are provided between a positive supply terminal 44 and a negative supply terminal 45 of the circuit 31.
A drain of the first MOSFET 41 is connected to the positive supply terminal 44 and is applied with a positive supply voltage +V.sub.dd. A source of the first MOSFET 41 is connected to a drain of the second MOSFET 42. A source of the second MOSFET 42 is connected to the negative supply terminal 45 and is applied with a negative supply voltage--V.sub.ss.
An output terminal 46 of the circuit 31 is connected to the connection point of the source of the first MOSFET 41 and the drain of the second MOSFET 42. A digital output signal Sc is taken out from the output terminal 46.
A gate of the first MOSFET 41 is directly connected to an input terminal 32 outside the circuit 31. This gate is applied with a first digital input signal Sa that is supplied into the input terminal 32.
A gate of the second MOSFET 42 is connected to the input terminal 32 through an inverter 34. A gate of the second MOSFET 42 is connected to an output end of the inverter 34. An input end of the inverter 34 is connected to the input terminal 32. The gate of the second MOSFET 42 is applied with a second digital input signal Sb. The second input signal Sb is produced by inverting the logic state of the first input signal Sa by the inverter 34.
The first input signal Sa is of a positive logic and the second input signal Sb is of a negative logic. Therefore, the second input signal Sb is always opposite in logic state to the first input signal Sa.
When the first input signal sa is in the high or "H" level, the second input signal Sb is in the low or "L" level. Therefore, the first enhancement MOSFET 41 is ON or conductive and the second enhancement MOSFET 42 is OFF or nonconductive and as a result, the output signal Sc is in the high or H level.
On the other hand, when the first input signal Sa is in the L level, the second input signal Sb is in the H level. Therefore, the first MOSFET 41 is OFF and the second MOSFET 42 is ON and as a result, the output signal Sc is in the L level.
Thus, if one of the first and second MOSFETs 41 and 42 is ON, the other thereof is always OFF, which means that none of the MOSFETs 41 and 42 are ON simultaneously. Accordingly, no current flows through the MOSFETs 41 and 42 in either steady state except for a leakage current of the MOSFET 41 or 42, resulting in low power dissipation.
The conventional output buffer circuit 31 described above has the following problem.
When the output signal Sc is turned from the L level to the H level, in other words, the first input signal Sa is turned from the L level to the H level, the first MOSFET 41 cannot be rapidly changed from the nonconductive state to the conductive state. Consequently, the circuit 31 cannot respond quickly to the rapid transition of the first input signal Sa because the output signal Sc is delayed to rise with respect to the first input signal Sa.
This problem is caused by the fact that the first MOSFET 41 needs to have the gate-to-source voltage V.sub.GS greater than its threshold voltage V.sub.TH in order to be turned on. The MOSFET 41 starts to be turned on after the delay in which the gate-to-source voltage V.sub.TH increases from the ground to the threshold voltage V.sub.TH and therefore, the output signal Sc starts to rise after the same delay.